CMOS devices are widely used as microprocessors, microcontrollers, random-access memorys (RAMs), high density image sensors and other digital logic circuits. A CMOS device has the advantages of high noise immunity and low static power consumption. However, due to hump phenomenon, concentrations of doped ions to control threshold voltage (Vth) of gate voltage (Vg) of the CMOS device is different between a tapered region and a flat region of a semiconductor layer which can be a poly-Si layer of the CMOS device. The different threshold voltages in different regions of the poly-Si layer of the CMOS device causes the CMOS device to have a high leakage current which is adverse to quality and operations of the CMOS device. Such high leakage current problem is more serious when the CMOS device is made smaller and smaller.
To overcome the high leakage current problem of the CMOS device due to the hump phenomenon, a concentration of ions in a tapered region of a poly-Si layer for an n-channel metal oxide semiconductor (NMOS) of the CMOS device needs to be increased, while the concentration of ions in a tapered region of a poly-Si layer for a p-channel metal oxide semiconductor (PMOS) thereof needs to be kept unchanged. To achieve this, an additional photo process is required during the manufacturing of the CMOS device. Such an additional photo process increases the manufacturing cost of the CMOS device.